1. Field of the Invention
The invention relates to the field of semiconductor metrology, and in particular, to methods and systems for performing metrology on sub-micron semiconductor structures.
2. Related Art
Modern semiconductor metrology techniques must deal with increasingly difficult measurement tasks as the dimensions of integrated circuits (ICs) continue to shrink. Consequently, metrology techniques that might have been acceptable for previous generations of ICs might not be able to handle the latest circuit designs.
For example, copper lines are formed during IC manufacturing as interconnects between devices. Typically, such lines are formed by etching trenches into a dielectric layer, forming an optional barrier layer in the trenches, overfilling those trenches with copper, and then performing chemical mechanical polishing (CMP) to remove the excess copper and create the fine copper lines.
To ensure proper IC functionality, the copper lines formed in this manner must meet strict dimensional requirements for line width and height (i.e., the CMP process must not remove an excessive amount of copper). These dimensional requirements include the requirement that the copper lines not include any voids (i.e., unfilled portions within the trenches) that can increase line resistance. Any barrier layers used in the formation of the copper lines (e.g., to enhance manufacturability, improve electrical performance, and/or reduce copper diffusion) and any subsequent enhancement layers (e.g., cobalt tungsten phosphide (CoWP) formed on top of copper lines to minimize copper diffusion and creep) must meet similar dimensional requirements. However, as the copper lines get increasingly smaller to minimize IC size and enable greater routing complexity, the conventional metrology methods for detecting voids and measuring line profiles (heights) begin to lose their effectiveness.
For example, a conventional method for measuring a patterned film is to direct an electron beam (e-beam) at the film and measure the intensity of the emitted x-rays. By scanning the e-beam over the pattern, the x-ray intensities for different locations in the pattern can be measured. Unfortunately, this method can be less than ideal for modern semiconductor wafers. For example, the e-beam typically spreads out as the beam enters the film. This e-beam “spread” can make the targeting of specific structures or portions of structures in the thin film impossible, thereby preventing conventional tools from being able to resolve the fine details of modern IC device structures. Furthermore, the need to scan the e-beam and take measurements at many locations over the wafer can undesirably increase the metrology time and reduce overall production throughput.
Accordingly, it is desirable to provide a system and method for accurately and efficiently measuring patterned films.